The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Feb. 09, 2018
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Xiao Sun, Austin, TX (US);

Wen Chen, Austin, TX (US);

Jayanta Bhadra, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3187 (2006.01); G01R 31/3183 (2006.01); G06F 11/27 (2006.01); G01R 31/317 (2006.01); G11C 29/44 (2006.01); G11C 29/12 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3187 (2013.01); G01R 31/31724 (2013.01); G01R 31/318364 (2013.01); G06F 11/27 (2013.01); G11C 29/44 (2013.01); G11C 29/56008 (2013.01); G11C 2029/1208 (2013.01);
Abstract

A method, system, and architecture () for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server () which receives specified hardware metric data () monitored at an integrated circuit device () in the field, identifies prioritized built-in self-test (BIST) fault detection tests () based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests () to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information () identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.


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