The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Jan. 16, 2017
Applicant:

Te Connectivity Corporation, Berwyn, PA (US);

Inventors:

Eric David Briant, Dillsburg, PA (US);

Randall Robert Henry, Lebanon, PA (US);

Brandon Michael Matthews, McAlisterville, PA (US);

James Charles Shiffler, Hershey, PA (US);

Charles Jameson Valentine, Lancaster, PA (US);

Leo Joseph Graham, Hershey, PA (US);

Assignee:

TE CONNECTIVITY CORPORATION, Berwyn, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 5/00 (2006.01); H01R 13/6594 (2011.01); H01R 12/70 (2011.01); H01R 12/58 (2011.01); H01R 13/518 (2006.01);
U.S. Cl.
CPC ...
H01R 13/6594 (2013.01); H01R 12/58 (2013.01); H01R 12/7005 (2013.01); H01R 13/518 (2013.01); H05K 5/00 (2013.01);
Abstract

A connector assembly includes a cage member having a plurality of walls defining a module cavity for a pluggable module. The walls include a top wall, a bottom wall and side walls extending between the top and bottom walls. The side walls extend to a bottom edge at the bottom wall and include mounting pins extending from the bottom edge that each have a press-fit portion configured to be press fit in a plated via of a circuit board. The bottom wall has a generally planar bottom surface facing the circuit board and a generally planar top surface facing the module cavity. The bottom wall includes a locating feature extending below the bottom surface and having a datum surface configured to engage the circuit board. The datum surface is a predetermined distance from the top surface to set a position of the top surface relative to the circuit board.


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