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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10490654 B1

PDFFull Text
Date of Patent:
Nov. 26, 2019

Filed:

Dec. 20, 2018

Vertical tunneling field-effect transistor cell and fabricating the same

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Harry-Hak-Lay Chuang, Singapore, SG;

Cheng-Cheng Kuo, Hsinchu, TW;

Chi-Wen Liu, Hsinchu, TW;

Ming Zhu, Singapore, SG;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Fernando L Toledo

Assistant Examiner:

Aaron J Gray

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/336 (2006.01); H01L 21/332 (2006.01); H01L 21/8238 (2006.01); H01L 29/739 (2006.01); H01L 21/265 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/324 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66977 (2013.01); H01L 21/26513 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/324 (2013.01); H01L 29/0653 (2013.01); H01L 29/42392 (2013.01); H01L 29/66356 (2013.01); H01L 29/66666 (2013.01); H01L 29/66742 (2013.01); H01L 29/7391 (2013.01); H01L 29/78618 (2013.01); H01L 29/78642 (2013.01); H01L 29/0657 (2013.01);
Abstract

Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.

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