The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Aug. 03, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abbas Ali, Plano, TX (US);

Guruvayurappan Mathur, Plano, TX (US);

Poornika Fernandes, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 49/02 (2006.01); H01L 29/06 (2006.01); H01L 27/07 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 27/0733 (2013.01); H01L 28/75 (2013.01); H01L 29/0653 (2013.01);
Abstract

An integrated circuit (IC) includes a substrate having a semiconductor surface layer, at least one capacitor above the semiconductor surface layer including a bottom plate, a capacitor dielectric over the bottom plate, and a top plate over the capacitor dielectric, functional circuitry in the semiconductor surface layer includes a core region having transistors configured together with the capacitor for realizing at least one circuit function. Electrically conductive metal filled contacts are through the dielectric layer that contact the top plate, the bottom plate, and the core region, including a first filled contact hole having a first depth and a first width that reach the top capacitor plate, and second filled contact hole having a second depth and a second width that reach the core region. The second depth is deeper than the first depth, and the first width is at least ten (10) % larger than the second width.


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