The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2019
Filed:
Aug. 30, 2017
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 21/56 (2006.01); H01L 21/027 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 23/315 (2013.01); H01L 21/0273 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81191 (2013.01);
Abstract
Conventional packages for 5G applications suffer from disadvantages including high mold stress on the die, reduced performance, and increased keep-out zone. To address these and other issues of the conventional packages, it is proposed to pre-apply a wafer-applied material, which remains in place, to form an air cavity between the die and the substrate. The air cavity can enhance the die's performance. Also, since the wafer-applied material can remain in place, the keep-out zone can be reduced. As a result, higher density modules can be fabricated.