The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Jun. 16, 2017
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Laurent Brunet, Grenoble, FR;

Nicolas Posseme, Sassenage, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8234 (2013.01); H01L 21/56 (2013.01); H01L 21/8221 (2013.01); H01L 24/83 (2013.01); H01L 27/0688 (2013.01); H01L 2224/8303 (2013.01); H01L 2924/1306 (2013.01);
Abstract

A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first transistor from a first semiconductor layer possibly made of silicon; encapsulating at least the first transistor with at least one first dielectric layer defining a first assembly; bonding a second dielectric layer located on the surface of a second semiconductor layer possibly made of silicon, to the first dielectric layer; depositing a planarizing material layer on the surface of the second semiconductor layer; selectively etching the planarizing material layer, to the second semiconductor layer; and producing at least one second transistor from the second semiconductor layer.


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