The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Aug. 23, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Takao Kamoshima, Hitachinaka, JP;

Kojiro Horita, Hitachinaka, JP;

Shuji Matsuo, Hitachinaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 27/11568 (2017.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/76805 (2013.01); H01L 21/76837 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H01L 27/11568 (2013.01); H01L 29/0649 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 21/76897 (2013.01);
Abstract

When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.


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