The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2019
Filed:
Nov. 30, 2018
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Masoud Zamani, San Diego, CA (US);
Bilal Zafar, Gladwyne, PA (US);
Venkatasubramanian Narayanan, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/22 (2006.01); H03K 5/133 (2014.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); H03K 5/133 (2013.01); H03K 19/20 (2013.01); H03K 2005/00019 (2013.01);
Abstract
A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.