The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Jun. 20, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Hiroki Murakami, Taichung, TW;

Hidemitsu Kojima, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 7/22 (2006.01); G11C 7/12 (2006.01); G11C 7/08 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G11C 7/08 (2013.01); G11C 7/12 (2013.01); G11C 16/26 (2013.01); G11C 16/3436 (2013.01); G11C 16/3459 (2013.01); G11C 2207/005 (2013.01); G11C 2207/2281 (2013.01);
Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a maintaining circuit, a sensing circuit, an output circuit, and a verification circuit. The maintaining circuit is configured to maintain data read from a memory cell array and output the data to a data bus in response to a column selection signal. The sensing circuit is configured to sense the data on the data bus in response to at least one sensing enable signal. The output circuit is configured to output the data sensed by the sensing circuit. The verification circuit is configured to verify an operation margin of the sensing circuit and output a verification result. The timing of the at least one sensing enable signal is set according to the verification result of the verification circuit.


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