The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Oct. 21, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David A. Koufaty, Portland, OR (US);

Gilbert Neiger, Hillsboro, OR (US);

Rajesh M. Sankaran, Portland, OR (US);

Andrew V. Anderson, Forest Grove, OR (US);

Subramanya R. Dulloor, Hillsboro, OR (US);

Werner Haas, Braunschweig, DE;

Joseph Nuzman, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/14 (2006.01); G06F 21/52 (2013.01);
U.S. Cl.
CPC ...
G06F 12/1466 (2013.01); G06F 21/52 (2013.01); G06F 2212/1052 (2013.01);
Abstract

A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.


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