The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Nov. 28, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert Valentine, Kiryat Tivon, IL;

Mark Charney, Lexington, MA (US);

Raanan Sade, Kibutz Sarid, IL;

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Jesus Corbal, King City, OR (US);

Roman S. Dubtsov, Novosibirsk, RU;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/49 (2006.01); G06F 9/302 (2018.01); G06F 9/22 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 7/48 (2006.01); G06F 9/345 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/3013 (2013.01); G06F 9/3016 (2013.01); G06F 7/4806 (2013.01); G06F 7/4812 (2013.01); G06F 9/30163 (2013.01); G06F 9/30167 (2013.01); G06F 9/345 (2013.01); G06F 9/382 (2013.01); G06F 9/3824 (2013.01);
Abstract

An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiply-accumulate of a first complex number, a second complex number, and a third complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder to decode an instruction to generate the decoded instruction and a first source register, a second source register, and a source and destination register to provide the first complex number, the second complex number, and the third complex number, respectively.


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