The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Apr. 13, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kuljit S. Bains, Olympia, WA (US);

John B. Halbert, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 8/12 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4097 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0605 (2013.01); G06F 3/0683 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); G06F 13/4295 (2013.01); G06F 15/7807 (2013.01); G11C 7/1003 (2013.01); G11C 7/1072 (2013.01); G11C 8/12 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4097 (2013.01); G11C 7/1021 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.


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