The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Jun. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Lakshminarayana Pappu, Folsom, CA (US);

Timothy J. Callahan, Hillsboro, OR (US);

Baruch Schnarch, Halfa, IL;

Hem Doshi, Folsom, CA (US);

Suketu U. Bhatt, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 13/42 (2006.01); G06F 11/30 (2006.01); G06F 21/85 (2013.01);
U.S. Cl.
CPC ...
H04L 63/083 (2013.01); G06F 11/30 (2013.01); G06F 13/4282 (2013.01);
Abstract

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; a transaction originator to originate a transactions and issue the transactions onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transactions at the serial IO interface via the device fabric and return responsive transactions to the device originator based on the transactions received; signature collection logic to collect signal information based on the transactions carried by the device fabric; and a signal accumulator to generate a test signature based on the signal information collected by the signature collection logic. Other related embodiments are disclosed.


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