The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Aug. 03, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Aman Bhatia, San Jose, CA (US);

Yi-Min Lin, San Jose, CA (US);

Naveen Kumar, San Jose, CA (US);

Johnson Yen, Fremont, CA (US);

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/29 (2006.01); H03M 13/37 (2006.01); H03M 13/39 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
H03M 13/2909 (2013.01); H03M 13/2927 (2013.01); H03M 13/2942 (2013.01); H03M 13/3746 (2013.01); H03M 13/3977 (2013.01); H03M 13/152 (2013.01);
Abstract

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.


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