The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

May. 16, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shih-Lien Linus Lu, Hsinchu, TW;

Cormac Michael O'Connell, Ontario, CA;

Kun-Hsi Li, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/003 (2006.01); G06F 17/50 (2006.01); G11C 11/419 (2006.01); H01L 23/00 (2006.01); H01L 21/324 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00315 (2013.01); G06F 17/5022 (2013.01); G06F 17/5081 (2013.01); G11C 11/419 (2013.01); H01L 21/324 (2013.01); H01L 23/576 (2013.01); H01L 27/1104 (2013.01);
Abstract

A physically unclonable function (PUF) device and a method for maximizing existing process variation for a physically unclonable device are provided. The method of maximizing process variation of the PUF device includes: modeling a physically unclonable function (PUF) device, comprising a plurality of PUF cells, selecting the size of transistors in the PUF device to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells, varying the material of the PUF device, and driving the PUF device with a predetermined voltage. The physically unclonable device includes: a plurality of PUF cells, configured to generate an output. Each of the plurality of PUF cells includes a harvester circuit, configured to generate a bit line and a complementary bit line. The harvester circuit is selected to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells; and a sense amplifier having a plurality of transistors configured to receive a first input signal and a second input signal from the harvester circuit.


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