The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2019
Filed:
Dec. 14, 2015
Applicant:
Hestia Power Inc., Hsinchu, TW;
Inventors:
Cheng-Tyng Yen, Hsinchu, TW;
Chien-Chung Hung, Hsinchu, TW;
Chwan-Ying Lee, Hsinchu, TW;
Lurng-Shehng Lee, Hsinchu, TW;
Assignee:
HESTIA POWER INC., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7806 (2013.01); H01L 29/0688 (2013.01); H01L 29/0696 (2013.01); H01L 29/1608 (2013.01); H01L 29/1095 (2013.01); H01L 29/45 (2013.01);
Abstract
A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.