The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2019
Filed:
Feb. 27, 2018
Applicant:
Mitsubishi Electric Corporation, Tokyo, JP;
Inventors:
Assignee:
Mitsubishi Electric Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/13 (2006.01); H01L 29/786 (2006.01); H01L 29/417 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 21/383 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/134363 (2013.01); G02F 1/136259 (2013.01); H01L 27/124 (2013.01); H01L 27/1251 (2013.01); H01L 27/1262 (2013.01); H01L 27/1285 (2013.01); H01L 29/41733 (2013.01); H01L 29/78669 (2013.01); G02F 1/13454 (2013.01); G02F 2001/134318 (2013.01); G02F 2001/134381 (2013.01); G02F 2001/136268 (2013.01); G02F 2202/10 (2013.01); G02F 2202/103 (2013.01); H01L 21/383 (2013.01); H01L 29/4908 (2013.01); H01L 29/66765 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01);
Abstract
An array substrate according to the present invention is a TFT substrate including a pixel TFT and a drive TFT on a substrate, where the pixel TFT includes a first source electrode, a first drain electrode, and an amorphous silicon layer, and the drive TFT includes a third oxide semiconductor layer provided on a gate insulating film while overlapping a second gate electrode in plan view, and a second source electrode and a second drain electrode overlapping the third oxide semiconductor layer in plan view, with a third separation portion separating the second source electrode and the second drain electrode from each other.