The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2019
Filed:
Feb. 18, 2014
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Chai Ean Gill, Chandler, AZ (US);
Changsoo Hong, Phoenix, AZ (US);
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/66 (2006.01); H01L 29/735 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0259 (2013.01); H01L 21/76283 (2013.01); H01L 29/0649 (2013.01); H01L 29/0808 (2013.01); H01L 29/0821 (2013.01); H01L 29/1008 (2013.01); H01L 29/6625 (2013.01); H01L 29/735 (2013.01);
Abstract
An area-efficient, low voltage ESD protection device () is provided for protecting low voltage pins () against ESD events by using one or more stacked low voltage NPN bipolar junction transistors, each formed in a p-type material with an N+ collector region () and P+ base region () formed on opposite sides of an N+ emitter region () with separate halo extension regions (-) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (It) and set the snapback voltage (Vsb) and triggering voltage (Vt) at the desired level.