The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Feb. 15, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shih-Lien Linus Lu, Hsinchu, TW;

Yu-Der Chih, Hsin-Chu, TW;

Chung-Cheng Chou, Hsin-Chu, TW;

Tong-Chern Ong, Chong-Her, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G06F 21/64 (2013.01); G06F 12/14 (2006.01); G06F 21/79 (2013.01); G11C 7/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0038 (2013.01); G06F 12/1425 (2013.01); G06F 21/64 (2013.01); G06F 21/79 (2013.01); G11C 13/0004 (2013.01); G11C 13/0059 (2013.01); G11C 13/0069 (2013.01); G11C 7/24 (2013.01); G11C 2013/0083 (2013.01); G11C 2213/79 (2013.01);
Abstract

A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state; and a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state.


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