The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Sep. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Karl I. Taht, Beaverton, OR (US);

Christopher B. Wilkerson, Portland, OR (US);

Ren Wang, Portland, OR (US);

James J. Greensky, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0831 (2016.01); G06F 12/0846 (2016.01); G06F 12/128 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0831 (2013.01); G06F 12/0848 (2013.01); G06F 12/128 (2013.01); G06F 2212/282 (2013.01); G06F 2212/621 (2013.01);
Abstract

Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.


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