Hardware interface component for processing write access requests that identify a register using lesser significant bits of a target address and identify an arithmetic operation to be performed using greater significant bits of the target address

Abstract

A hardware interface component arranged to operably couple at least one arithmetic unit to a an interconnect component of a processing system. The hardware interface component comprises a plurality of program-visible registers and at least one operation decoder component. The at least one operation decoder component is arranged to, upon receipt of a write access request via the interconnect component corresponding to a decorated memory-mapped address range for the hardware interface component, decode a register identifier component of a target address of the received write access request to identify at least one of the program-visible registers, decode a decoration component of the target address of the received write access request to identify an arithmetic operation to be performed, and configure the arithmetic unit to perform the identified arithmetic operation on at least one input operand within the identified at least one program-visible register.