The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Mar. 05, 2018
Applicant:

Laird Technologies, Inc., Earth City, MO (US);

Inventors:

Jason L. Strader, Cleveland, OH (US);

Eugene Anthony Pruss, Avon Lake, OH (US);

Gerald R. English, Glen Ellyn, IL (US);

Assignee:

Laird Technologies, Inc., Chesterfield, MO (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 9/00 (2006.01); H05K 1/03 (2006.01); H05K 3/32 (2006.01); H05K 3/46 (2006.01); B32B 37/20 (2006.01);
U.S. Cl.
CPC ...
H05K 9/0024 (2013.01); H05K 1/0393 (2013.01); H05K 3/321 (2013.01); H05K 3/4655 (2013.01); H05K 3/4658 (2013.01); H05K 3/4691 (2013.01); H05K 9/0084 (2013.01); B32B 37/206 (2013.01); B32B 2309/02 (2013.01); B32B 2309/12 (2013.01); H05K 2201/0195 (2013.01); H05K 2201/0715 (2013.01);
Abstract

A multilayer board level shield includes an electrically-conductive shielding layer disposed between inner and outer dielectric layers. The multilayer board level shield may have an overall thickness of about 25 microns or less. The multilayer board level shield may have sufficient flexibility to be reconfigurable generally over one or more components on a substrate to thereby provide board level shielding for the one or more components. One or more dielectric joints may be defined between the printed circuit board and the outer dielectric layer that attach the multilayer board level shield to the printed circuit board.


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