The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Jun. 15, 2018
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Hyangkeun Yoo, Icheon-si, KR;
Joong Sik Kim, Yongin-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/1159 (2017.01); H01L 29/51 (2006.01); H01L 29/08 (2006.01); G11C 11/22 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1159 (2013.01); G11C 11/223 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); H01L 21/28291 (2013.01); H01L 29/0847 (2013.01); H01L 29/513 (2013.01); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09);
Abstract
A ferroelectric memory device includes a substrate, an interfacial insulation layer disposed on the substrate, a recombination induction layer disposed on the interfacial insulation layer, a ferroelectric layer disposed on the recombination induction layer, and a gate electrode disposed on the ferroelectric layer. The recombination induction layer includes a material containing holes acting as a majority carrier.