The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Jan. 18, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Vikas Gupta, Dallas, TX (US);

Daniel Yong Lin, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49579 (2013.01); H01L 23/3107 (2013.01); H01L 23/3142 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49575 (2013.01); H01L 23/49582 (2013.01); H01L 23/49586 (2013.01); H01L 23/49541 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/80815 (2013.01); H01L 2924/181 (2013.01);
Abstract

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.


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