The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Sep. 21, 2018
Applicant:

United Microelectronics Corporation, Hsinchu, TW;

Inventors:

Yan-Da Chen, Taipei, TW;

Weng Yi Chen, Zhubei, TW;

Chang-Sheng Hsu, Hsinchu, TW;

Kuan-Yu Wang, New Taipei, TW;

Yuan Sheng Lin, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); B81C 1/00 (2006.01); H01L 23/31 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02107 (2013.01); B81C 1/00801 (2013.01); B81B 2207/015 (2013.01); B81C 2201/014 (2013.01); B81C 2201/016 (2013.01); H01L 21/76829 (2013.01); H01L 23/3171 (2013.01);
Abstract

Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.


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