The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Jun. 05, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Ping-Kun Wang, Taichung, TW;

Shao-Ching Liao, Taichung, TW;

Ming-Che Lin, Taichung, TW;

Min-Chih Wei, Taichung, TW;

Chuan-Sheng Chou, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0097 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 2013/009 (2013.01); G11C 2013/0045 (2013.01); G11C 2213/15 (2013.01); G11C 2213/31 (2013.01); G11C 2213/52 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/143 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01);
Abstract

A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.


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