The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Apr. 05, 2016
Applicant:

Via Alliance Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

G. Glenn Henry, Austin, TX (US);

Terry Parks, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06N 3/063 (2006.01); G06F 9/38 (2018.01); G06F 15/82 (2006.01); G06F 1/10 (2006.01); G06N 3/04 (2006.01); G06F 9/445 (2018.01); G06N 3/08 (2006.01); G06F 7/499 (2006.01); G06F 7/483 (2006.01); G06F 9/32 (2018.01);
U.S. Cl.
CPC ...
G06F 15/82 (2013.01); G06F 1/10 (2013.01); G06F 7/483 (2013.01); G06F 7/49947 (2013.01); G06F 9/3001 (2013.01); G06F 9/3004 (2013.01); G06F 9/30029 (2013.01); G06F 9/30032 (2013.01); G06F 9/30098 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/321 (2013.01); G06F 9/38 (2013.01); G06F 9/3836 (2013.01); G06F 9/3867 (2013.01); G06F 9/3877 (2013.01); G06F 9/3893 (2013.01); G06F 9/44505 (2013.01); G06N 3/04 (2013.01); G06N 3/0445 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); G06N 3/0635 (2013.01); G06N 3/08 (2013.01); G06N 3/088 (2013.01);
Abstract

A processor has functional units that fetch and decode architectural instructions of an architectural instruction set at a first rate, a register that stores a value of an indicator programmable by execution of an architectural instruction of the architectural instruction set, and an execution unit. The execution unit includes a first memory that holds data, a second memory that holds instructions of a program, and a plurality of processing units that execute the program instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory. The instructions are of an instruction set that is distinct from the architectural instruction set. The second rate is the first rate when the indicator is programmed with a first value and the second rate is less than the first rate when the indicator is programmed with a second value.


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