The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Sep. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bahaa Fahim, Santa Clara, CA (US);

Min Huang, Cupertino, CA (US);

Zhiguo Wang, Palo Alto, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 12/0811 (2016.01); G11C 29/44 (2006.01); G11C 29/00 (2006.01); G06F 12/0868 (2016.01); G06F 12/0875 (2016.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1064 (2013.01); G06F 12/0811 (2013.01); G06F 12/0868 (2013.01); G06F 12/0875 (2013.01); G11C 29/4401 (2013.01); G11C 29/70 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/283 (2013.01); G11C 29/52 (2013.01); G11C 2029/0409 (2013.01);
Abstract

A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.


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