The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10474375 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 12, 2019

Filed:

Dec. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kermin Elliott Fleming, Jr., Hudson, MA (US);

Simon C. Steely, Jr., Hudson, NH (US);

Kent D. Glossop, Nashua, NH (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/00 (2006.01); G06F 13/16 (2006.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 9/30043 (2013.01); G06F 9/3826 (2013.01); G06F 9/3834 (2013.01); G06F 12/00 (2013.01); G06F 13/16 (2013.01);
Abstract

An integrated circuit includes a processor to execute instructions and to interact with memory, and acceleration hardware, to execute a sub-program corresponding to instructions. A set of input queues includes a store address queue to receive, from the acceleration hardware, a first address of the memory, the first address associated with a store operation and a store data queue to receive, from the acceleration hardware, first data to be stored at the first address of the memory. The set of input queues also includes a completion queue to buffer response data for a load operation. A disambiguator circuit, coupled to the set of input queues and the memory, is to, responsive to determining the load operation, which succeeds the store operation, has an address conflict with the first address, copy the first data from the store data queue into the completion queue for the load operation.


Find Patent Forward Citations

Fleming, Jr., Kermin. (2019). Runtime address disambiguation in acceleration hardware (U.S. Patent No. 10474375). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10474375

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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