The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Mar. 31, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Daniel G. Cartagena, Chandler, AZ (US);
Corey D. Gough, Hillsboro, OR (US);
Vivek Garg, Folsom, CA (US);
Nikhil Gupta, Hillsboro, OR (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/20 (2006.01); G06F 1/32 (2019.01); G06F 1/3206 (2019.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G06F 1/206 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 1/3296 (2013.01); Y02D 10/126 (2018.01); Y02D 10/16 (2018.01); Y02D 10/172 (2018.01);
Abstract
A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.