The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Nov. 09, 2017
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Yu-Ming Chen, Taichung, TW;

Yi-Der Wu, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B29C 41/02 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01); H05K 3/40 (2006.01); B29C 64/30 (2017.01); B33Y 80/00 (2015.01); B29C 64/129 (2017.01); B29C 64/386 (2017.01); B29C 64/124 (2017.01); B29C 64/112 (2017.01); B29C 64/393 (2017.01); H05K 3/12 (2006.01); B29C 64/118 (2017.01); B29L 31/34 (2006.01); B33Y 10/00 (2015.01);
U.S. Cl.
CPC ...
H05K 3/4664 (2013.01); B29C 64/112 (2017.08); B29C 64/118 (2017.08); B29C 64/124 (2017.08); B29C 64/129 (2017.08); B29C 64/30 (2017.08); B29C 64/386 (2017.08); B29C 64/393 (2017.08); B33Y 80/00 (2014.12); H05K 3/0011 (2013.01); H05K 3/0014 (2013.01); H05K 3/12 (2013.01); H05K 3/4053 (2013.01); H05K 3/4076 (2013.01); H05K 3/465 (2013.01); H05K 3/467 (2013.01); H05K 3/4644 (2013.01); B29L 2031/3425 (2013.01); B33Y 10/00 (2014.12); H05K 3/125 (2013.01); H05K 2203/163 (2013.01);
Abstract

A manufacturing method of a circuit board includes: performing a first printing process to form a first insulating layer having a first circuit depressed pattern; performing a second printing process to form a first circuit layer in the first circuit depressed pattern; checking whether a real position of the first circuit layer is diverged from a predetermined position; determining whether the shift level of the position of the first circuit layer is more than a predetermined level; performing the first printing process to form the second insulating layer, wherein when the shift level is more than the predetermined level and the thickness of a second insulating layer to be formed on the first insulating layer is not greater than a tolerance thickness, the second insulating layer has a hole at least partially overlapping the real position; and performing the second printing process to form a conductive plug in the hole.


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