The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Dec. 28, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mark Schmisseur, Phoenix, AZ (US);

Dimitrios Ziakas, Hillsboro, OR (US);

Murugasamy K. Nachimuthu, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/08 (2006.01); G06F 3/06 (2006.01); G11C 29/36 (2006.01); G11C 29/38 (2006.01); G11C 29/44 (2006.01); G06F 16/22 (2019.01); G06F 16/2455 (2019.01); G06F 12/02 (2006.01); G06F 12/14 (2006.01); G06F 13/16 (2006.01); G06F 15/173 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 9/448 (2018.01); G06F 9/28 (2006.01); G06F 15/16 (2006.01); H04L 12/24 (2006.01); H04L 29/06 (2006.01); H04L 29/08 (2006.01); H04L 12/703 (2013.01); H04L 12/743 (2013.01); H04L 12/801 (2013.01); H04L 12/803 (2013.01); H04L 12/935 (2013.01); H04L 12/931 (2013.01); G06F 9/4401 (2018.01); G06F 9/445 (2018.01); G06F 12/06 (2006.01); G06F 16/23 (2019.01); G06F 16/248 (2019.01); G06F 16/901 (2019.01); G06F 9/50 (2006.01); G06F 17/50 (2006.01); G06F 16/25 (2019.01); G06F 16/2453 (2019.01); G06F 16/11 (2019.01); H04L 12/861 (2013.01); G11C 8/12 (2006.01); G11C 29/02 (2006.01); G06F 12/0802 (2016.01); G06F 12/1045 (2016.01);
U.S. Cl.
CPC ...
H04L 9/0819 (2013.01); G06F 3/0604 (2013.01); G06F 3/065 (2013.01); G06F 3/0605 (2013.01); G06F 3/067 (2013.01); G06F 3/0611 (2013.01); G06F 3/0613 (2013.01); G06F 3/0629 (2013.01); G06F 3/0631 (2013.01); G06F 3/0632 (2013.01); G06F 3/0644 (2013.01); G06F 3/0647 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01); G06F 3/0685 (2013.01); G06F 9/28 (2013.01); G06F 9/445 (2013.01); G06F 9/4406 (2013.01); G06F 9/4411 (2013.01); G06F 9/4494 (2018.02); G06F 9/5044 (2013.01); G06F 9/5088 (2013.01); G06F 12/023 (2013.01); G06F 12/06 (2013.01); G06F 12/0607 (2013.01); G06F 12/14 (2013.01); G06F 13/1663 (2013.01); G06F 13/1668 (2013.01); G06F 13/4068 (2013.01); G06F 13/42 (2013.01); G06F 15/161 (2013.01); G06F 15/17331 (2013.01); G06F 16/119 (2019.01); G06F 16/221 (2019.01); G06F 16/2237 (2019.01); G06F 16/2255 (2019.01); G06F 16/2282 (2019.01); G06F 16/2365 (2019.01); G06F 16/248 (2019.01); G06F 16/2453 (2019.01); G06F 16/2455 (2019.01); G06F 16/24553 (2019.01); G06F 16/25 (2019.01); G06F 16/9014 (2019.01); G06F 17/5054 (2013.01); G11C 8/12 (2013.01); G11C 29/028 (2013.01); G11C 29/36 (2013.01); G11C 29/38 (2013.01); G11C 29/44 (2013.01); H04L 9/0894 (2013.01); H04L 41/0213 (2013.01); H04L 41/0668 (2013.01); H04L 41/0677 (2013.01); H04L 41/0893 (2013.01); H04L 41/0896 (2013.01); H04L 45/28 (2013.01); H04L 45/7453 (2013.01); H04L 47/11 (2013.01); H04L 47/125 (2013.01); H04L 49/30 (2013.01); H04L 49/351 (2013.01); H04L 49/9005 (2013.01); H04L 69/12 (2013.01); H04L 69/22 (2013.01); H04L 69/32 (2013.01); H04L 69/321 (2013.01); G06F 12/0802 (2013.01); G06F 12/1054 (2013.01); G06F 12/1063 (2013.01); G06F 2201/85 (2013.01); G06F 2209/509 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/601 (2013.01); G06F 2213/0064 (2013.01);
Abstract

Technologies for efficiently managing the allocation of memory in a shared memory pool include a memory sled. The memory sled includes a memory pool of byte-addressable memory devices. The memory sled also includes a memory pool controller coupled to the memory pool. The memory pool controller receives a request to provision memory to a compute sled. Further, the memory pool controller maps, in response to the request, each of the memory devices of the memory pool to the compute sled. The memory pool controller additionally assigns access rights to the compute sled as a function of one or more memory characteristics of the compute sled. The memory characteristics are indicative of an amount of memory in the memory pool to be used by the compute sled and the access rights are indicative of access permissions to one or more memory address ranges associated with the one or more memory devices.


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