The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2019
Filed:
Dec. 12, 2014
Ams Ag, Unterpremstaetten, AT;
Franz Schrank, Graz, AT;
Sara Carniello, Graz, AT;
Hubert Enichlmair, Weinitzen, AT;
Jochen Kraft, Oberaich, AT;
Bernhard Loeffler, Gleisdorf, AT;
Rainer Holzhaider, Graz, AT;
ams AG, Unterpremstaetten, AT;
Abstract
A dielectric layer () is arranged on the main surface () of a semiconductor substrate (), and a passivation layer () is arranged on the dielectric layer. A metal layer () is embedded in the dielectric layer above an opening () in the substrate, and a metallization () is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface () of the substrate. A layer or layer sequence () comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug () may additionally be arranged in the opening without filling the opening.