The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2019
Filed:
Dec. 06, 2018
United Microelectronics Corp., Hsin-Chu, TW;
Chun-Ting Chiang, Kaohsiung, TW;
Chi-Ju Lee, Tainan, TW;
Chih-Wei Lin, Kaohsiung, TW;
Bo-Yu Su, Tainan, TW;
Yen-Liang Wu, Taipei, TW;
Wen-Tsung Chang, Tainan, TW;
Jui-Ming Yang, Taichung, TW;
I-Fan Chang, Hsinchu, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.