The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Aug. 04, 2016
Applicant:

Sumitomo Heavy Industries Ion Technology Co., Ltd., Tokyo, JP;

Inventors:

Tetsuya Kudo, Ehime, JP;

Shinji Ebisu, Ehime, JP;

Yoshito Fujii, Ehime, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/677 (2006.01); C23C 14/48 (2006.01); H01L 21/68 (2006.01); H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67778 (2013.01); C23C 14/48 (2013.01); H01L 21/67196 (2013.01); H01L 21/67201 (2013.01); H01L 21/67213 (2013.01); H01L 21/67742 (2013.01); H01L 21/67745 (2013.01); H01L 21/67748 (2013.01); H01L 21/67766 (2013.01); H01L 21/68 (2013.01); H01L 21/68764 (2013.01); H01J 2237/184 (2013.01); H01J 2237/204 (2013.01); H01J 2237/20207 (2013.01); H01J 2237/31701 (2013.01);
Abstract

A first conveyance mechanism and a second conveyance mechanism convey a pair of two wafers to an alignment device from a wafer container via a buffer device, and then bring the wafers respectively into a first load lock chamber and a second load lock chamber after alignment. An intermediate conveyance mechanism conveys one of the pair of two wafers between the first load lock chamber and a vacuum processing chamber. The intermediate conveyance mechanism conveys the other of the pair of two wafers between the second load lock chamber and the vacuum processing chamber. The first conveyance mechanism and the second conveyance mechanism take out the pair of two wafers subjected to an implantation process from the first load lock chamber and the second load lock chamber and store the wafers into the wafer container.


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