The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Sep. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Helia Naeimi, Santa Clara, CA (US);

Qi Zeng, Santa Clara, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0811 (2016.01); G06F 12/128 (2016.01); G06F 12/0888 (2016.01); G06F 12/084 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/084 (2013.01); G06F 12/0888 (2013.01); G06F 12/128 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/283 (2013.01); G06F 2212/621 (2013.01);
Abstract

Provided are an apparatus, system, integrated circuit die, and method for caching data in a hierarchy of caches. A first cache line in a first level cache having modified data for an address is processed. Each cache line of cache lines in the first level cache store data for one of a plurality of addresses stored in multiple cache lines of a second level cache. A second cache line in the second level cache is selected and a determination is made of a number of corresponding bits in the first cache line and the second cache line that are different. Bits in the first cache line that are different from the corresponding bits in the second cache line are written to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.


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