The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Mar. 21, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Krishnaprasad H, Bangalore, IN;

Ramkumar Jayaraman, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 9/445 (2018.01); G06F 9/4401 (2018.01); G06F 9/48 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 9/44557 (2013.01); G06F 3/0604 (2013.01); G06F 3/0632 (2013.01); G06F 3/0683 (2013.01); G06F 9/4403 (2013.01); G06F 9/4406 (2013.01); G06F 9/4843 (2013.01);
Abstract

Technologies for reliable software execution include a computing device having a memory that includes multiple ranks. The computing device trains the ranks of the memory and determines a consolidated memory score for each rank. Each consolidated memory score is indicative of a margin of the corresponding rank. The computing device identifies a higher-margin address range using the consolidated memory scores. The higher-margin memory address range is mapped to a higher-margin memory rank. The computing device loads high-priority software into the higher-margin memory address range. The high-priority software may include an operating system or a critical application. A pre-boot firmware environment may publish the consolidated memory scores to a higher-level software component, such as the operating system. The pre-boot firmware environment may map a predetermined address range to the higher-margin memory rank. A critical application may request to be loaded into a higher-margin address range. Other embodiments are described and claimed.


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