The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Dec. 29, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Eliezer Weissmann, Haifa, IL;

Karthikeyan Karthik Vaithianathan, Bangalore, IN;

Yoav Zach, Karkur, IL;

Boris Ginzburg, Haifa, IL;

Ronny Ronen, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 12/1027 (2016.01); G06F 12/1009 (2016.01); G06F 12/1081 (2016.01); G06F 12/1072 (2016.01); G06F 12/0875 (2016.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06F 12/1045 (2016.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3851 (2013.01); G06F 9/3881 (2013.01); G06F 9/3887 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0875 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 12/1045 (2013.01); G06F 12/1072 (2013.01); G06F 12/1081 (2013.01); G06F 3/0646 (2013.01); G06F 3/0662 (2013.01); G06F 3/0668 (2013.01); G06F 12/0292 (2013.01); G06F 12/145 (2013.01); G06F 12/1441 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/283 (2013.01); G06F 2212/302 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/62 (2013.01); G06F 2212/65 (2013.01); G06F 2212/68 (2013.01); G06F 2212/683 (2013.01); G06F 2212/684 (2013.01);
Abstract

An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.


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