The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Aug. 16, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chun-Yang Tsai, Hsinchu, TW;

Kuo-Ching Huang, Hsinchu, TW;

Tong-Chern Ong, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 21/336 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2436 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H01L 45/1253 (2013.01); G11C 2013/0042 (2013.01); G11C 2013/0071 (2013.01); G11C 2013/0073 (2013.01); G11C 2013/0088 (2013.01); G11C 2213/71 (2013.01); G11C 2213/78 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01);
Abstract

The present disclosure relates to a memory circuit having a shared control device for access to target and complementary memory devices for improved differential sensing. The memory circuit has a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal. A first memory device has a first lower electrode separated from a first upper electrode by a first data storage layer. The first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line. A second memory device has a second lower electrode separated from a second upper electrode by a second data storage layer. The second upper electrode is coupled to the second bit-line and the second lower electrode is coupled to the third terminal.


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