The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Jan. 26, 2017
Applicant:

Hiroshi Watanabe, Yokohama-shi, Kanagawa-ken, JP;

Inventors:

Yukihiro Nagai, Sapporo, JP;

Hiroshi Watanabe, Yokohama, JP;

Riichiro Shirota, Fujisawa, JP;

Assignee:

Other;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/34 (2006.01); G11C 29/02 (2006.01); G11C 29/00 (2006.01); G06F 21/57 (2013.01); G11C 29/18 (2006.01); G06F 21/44 (2013.01); G06F 21/73 (2013.01); G11C 7/24 (2006.01); G09C 1/00 (2006.01); G11C 29/12 (2006.01); G11C 29/16 (2006.01); G11C 29/24 (2006.01); G11C 29/26 (2006.01); G11C 29/36 (2006.01); G11C 29/44 (2006.01); G11C 29/56 (2006.01); H04L 9/08 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
G11C 29/34 (2013.01); G06F 21/44 (2013.01); G06F 21/577 (2013.01); G06F 21/73 (2013.01); G09C 1/00 (2013.01); G11C 7/24 (2013.01); G11C 29/022 (2013.01); G11C 29/025 (2013.01); G11C 29/027 (2013.01); G11C 29/1201 (2013.01); G11C 29/16 (2013.01); G11C 29/18 (2013.01); G11C 29/24 (2013.01); G11C 29/26 (2013.01); G11C 29/36 (2013.01); G11C 29/44 (2013.01); G11C 29/56008 (2013.01); G11C 29/78 (2013.01); G11C 29/783 (2013.01); H04L 9/0866 (2013.01); H04L 9/3278 (2013.01); G06F 2221/034 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/1806 (2013.01); G11C 2029/4402 (2013.01); G11C 2029/5606 (2013.01); H04L 2209/12 (2013.01);
Abstract

A semiconductor apparatus includes a semiconductor chip, with the semiconductor chip including a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses is randomly formed related to a part or an entirety of the modular area of the modular region. The distribution of the retrieved redundant addresses is irreversible, with a random number representing physical properties intrinsic to the semiconductor chip and providing copy protection. When another semiconductor chip uses the distribution of the retrieved redundant addresses the another semiconductor chip will malfunction. The test circuit outputs a random number generated from the distribution of the retrieved redundant addresses according to a specification code received from a physical-chip-identification measuring device.


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