The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Aug. 07, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Heng Cao, Shanghai, CN;

Sheng Fen Chiu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 29/861 (2006.01); H01L 45/00 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0097 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); H01L 27/2409 (2013.01); H01L 27/2463 (2013.01); H01L 29/861 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); G11C 2013/005 (2013.01); G11C 2013/009 (2013.01); G11C 2213/32 (2013.01); G11C 2213/52 (2013.01); G11C 2213/72 (2013.01); H01L 29/0649 (2013.01); H01L 45/1253 (2013.01);
Abstract

Semiconductor devices and fabrication methods thereof are provided to form a memory cell. The memory cell includes a first diode, a second diode separated from the first diode. The first diode includes a first well region in a substrate, a first N-type doped region adjacent to the first well region and connected to a bit line, and a first P-type doped region adjacent to the first well region and separated from the first N-type doped region. The second diode includes a second well region in the substrate, a second N-type doped region adjacent to the second well region, and a second P-type doped region. The memory cell further includes a bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively, a top electrode connected to a word line, and a data storage material layer located between the bottom electrode and the top electrode.


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