The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Jan. 16, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Bong-Kil Jung, Seoul, KR;

Hyunggon Kim, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0688 (2013.01); G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 12/0246 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/3459 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01);
Abstract

A nonvolatile memory device includes a nonvolatile memory cell array, where N bits are stored in a single memory cell (N being an integer greater than or equal to 2), and a page buffer circuit electrically connected to the nonvolatile memory cell array. The page buffer circuit includes at least N latches configured to temporarily store data. A data input/output circuit connected to the page buffer circuit receives programmed input data and provides the input data to the page buffer circuit. A control logic controls the page buffer and initializes a target latch value before receiving all input data of a program unit from the data input/output circuit.


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