The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2019
Filed:
Jan. 03, 2019
Applicant:
Esilicon Corporation, San Jose, CA (US);
Inventors:
Assignee:
eSilicon Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/34 (2006.01); H03M 1/40 (2006.01); H03M 1/36 (2006.01); H03M 1/46 (2006.01); H03M 1/00 (2006.01); H03M 1/12 (2006.01); H03M 1/06 (2006.01); H03M 1/10 (2006.01);
U.S. Cl.
CPC ...
H03M 1/40 (2013.01); H03M 1/368 (2013.01); H03M 1/462 (2013.01); H03M 1/00 (2013.01); H03M 1/06 (2013.01); H03M 1/1009 (2013.01); H03M 1/12 (2013.01); H03M 1/365 (2013.01); H03M 2201/2266 (2013.01);
Abstract
A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.