The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2019
Filed:
Oct. 31, 2017
Crossbar, Inc., Santa Clara, CA (US);
Hagop Nazarian, San Jose, CA (US);
Harry Yue Gee, Santa Clara, CA (US);
Crossbar, Inc., Santa Clara, CA (US);
Abstract
A logical NAND memory architecture comprising two-terminal, non-volatile resistive memory is disclosed. By way of example, disclosed logical NAND architectures can comprise non-volatile memory cells having approximately 4Farea. This facilitates very high memory densities, even for advanced technology nodes. Further, the disclosed architectures are CMOS compatible, and can be constructed among back-end-of-line (BEOL) metal layers of an integrated chip. In some embodiments, subsets of two-terminal memory cells in a NAND array can be constructed between different pairs of BEOL metal layers. In other embodiments, the two-terminal memory cells can be constructed between a single pair of BEOL metal layers.