The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2019
Filed:
Mar. 28, 2018
Applicant:
Sandisk Technologies Llc, Plano, TX (US);
Inventors:
Assignee:
SanDisk Technologies LLC, Addison, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1159 (2017.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H01L 27/1157 (2017.01); G11C 11/22 (2006.01); H01L 29/788 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 27/11582 (2017.01); H01L 27/11587 (2017.01); H01L 27/11597 (2017.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1159 (2013.01); G11C 11/223 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 29/788 (2013.01); H01L 29/78391 (2014.09); H01L 29/792 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01); H01L 27/11587 (2013.01); H01L 27/11597 (2013.01);
Abstract
A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel. The tunneling layer is disposed between the control gate and the charge storage region, the charge storage region is disposed between the tunneling layer and the blocking layer, and the blocking layer is disposed above the semiconductor channel.