The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2019
Filed:
May. 08, 2017
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventor:
Chih-Hao Lin, Taichung, TW;
Assignee:
Winbond Electronics Corp., Taichung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 27/108 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 23/58 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10814 (2013.01); H01L 21/76802 (2013.01); H01L 23/585 (2013.01); H01L 27/092 (2013.01); H01L 27/10855 (2013.01); H01L 27/10873 (2013.01); H01L 27/10891 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 29/66545 (2013.01); H01L 21/823842 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/6659 (2013.01);
Abstract
A manufacturing method of a dynamic random access memory (DRAM) structure includes following steps. A substrate is provided, wherein the substrate includes a memory cell region and a peripheral circuit region. A DRAM is formed in the memory cell region and includes a capacitor contact coupled to a capacitor structure. A transistor structure with a metal gate structure is formed in the peripheral circuit region. The metal gate structure is formed by a manufacturing process using a dummy gate. The capacitor contact and the dummy gate are formed by the same conductive layer.