The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Dec. 10, 2014
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Jianan Yang, Austin, TX (US);

Brad J. Garni, Austin, TX (US);

Shayan Zhang, Cedar Park, TX (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/12 (2006.01);
U.S. Cl.
CPC ...
G11C 17/12 (2013.01);
Abstract

A read only memory (ROM) having a first row of ROM cells, a first conductive line along the first row of ROM cells, and a second conductive line along the first row of ROM cells. The ROM cells of the first row of ROM cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the ROM the first row of ROM cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of ROM cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows.


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