The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Jan. 03, 2019
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Anirudh R. Acharya, San Diego, CA (US);

Swapnil Sakharshete, San Diego, CA (US);

Michael Mantor, Orlando, FL (US);

Mangesh P. Nijasure, Orlando, FL (US);

Todd Martin, Orlando, FL (US);

Vineet Goel, San Diego, CA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/00 (2011.01); G06T 1/20 (2006.01); G06T 15/80 (2011.01); G06F 9/50 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06T 15/005 (2013.01); G06F 9/4831 (2013.01); G06F 9/505 (2013.01); G06T 1/20 (2013.01); G06T 15/80 (2013.01);
Abstract

Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.


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