The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2019
Filed:
Mar. 31, 2017
Cadence Design Systems, Inc., San Jose, CA (US);
Karun Sharma, Fremont, CA (US);
Nikhil Garg, Haryana, IN;
Juno Jui-Chuan Lin, Saratoga, CA (US);
Subhashis Mandal, Noida, IN;
Chandra Prakash Manglani, Noida, IN;
Kanaka Raju Gorle, Nodia, IN;
Henry Yu, Palo Alto, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.