Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register

Abstract

A processor may include a programmable memory prefetcher that includes a programmable hardware prefetch engine and a prefetch engine control register. The programmable memory prefetcher may include circuitry and may be configured to receive, during execution of an application, a first instruction for configuring the prefetch engine for prefetching multiple cache lines to be accessed in the future, at predictable locations, by the application; to store, in the prefetch engine control register, dependent on information in the first instruction, data representing an amount of prefetching to be performed, and data representing a stride distance between consecutive cache lines to be prefetched; to receive a second instruction for prefetching a single cache line whose location is identified in the second instruction; and to initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the prefetch engine, to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register. The prefetch engine control register may store multiple entries, each including an identifier of a given operation to prefetch multiple cache lines. An instruction may also be received to disable prefetching of multiple cache lines. The multiple cache lines may be prefetched from a last-level cache (LLC) to a mid-level cache.